Speccy monitor state unsafe7/12/2023 ![]() ![]() This means that we can trigger VSP using one of 56 methods (eight different The specific 3-bit value that is written to YSCROLL, as well as the 3-bit value Plenty of trial-and-error, I could observe the following: The timing depends on Based on a combination of educated guesswork, luck and I wanted to investigate whether there were other ways of controlling the timing Triggered by setting the DEN bit instead of modifying YSCROLL. We also knew that the undefined value could be delayed slightly if VSP was On several factors including temperature. The relative timing of the undefined value and RAS depends The RAS signal, every memory cell with an xxx7 or xxxf address is at risk of Place a logically undefined value on the DRAM address lines during the Welcome to our latest new user Skuggan ! (Registered )įirst off, this is what we already knew: VSP causes the VIC chip to briefly
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